module ysyx_050369_wb (
    input            clk,
    input            rst,
    input            wb_ready,
    input            as2wb_valid,
    input [31:0]     i_inst,
`ifndef ysyx_050369_SOC
    input [31:0]     i_pc,
    input            i_dev,
`endif
    input [63:0]     i_reg_wdata,
    input            i_reg_wen,
    input [4:0]      i_reg_waddr,
    input [4:0]      i_rs1,
    input [4:0]      i_rs2,
    output [63:0]    o_rd1,
    output [63:0]    o_rd2,
    output           o_fence_i
);
    // wire mret_flag;
`ifndef ysyx_050369_SOC
    reg [31:0]  pc,inst;
    reg         dev;
`endif 
    reg [4:0]   reg_waddr;
    reg         reg_wen;
    wire [63:0] rd1,rd2;
    reg  [63:0] wdata;
    wire reg_wen_w;
    assign o_rd1 = ((|i_rs1)&&(i_rs1 == reg_waddr)&&reg_wen)?wdata:rd1;
    assign o_rd2 = ((|i_rs2)&&(i_rs2 == reg_waddr)&&reg_wen)?wdata:rd2;
    assign o_fence_i = i_inst == `ysyx_050369_FENCE;
`ifdef ysyx_050369_SOC
    assign reg_wen_w = reg_wen &&(wb_ready);
`else
    assign reg_wen_w = reg_wen &&o_run;
`endif 
    always @(posedge clk) begin
        if (rst) begin
            wdata       <= 'b0;
            reg_wen     <= 'b0;
            reg_waddr   <= 'b0;
        `ifndef ysyx_050369_SOC
            pc          <=  32'h80000000;
            inst        <= 'b0;
            dev         <= 'b0;
        `endif 
        end
        else begin
            if (as2wb_valid&&wb_ready) begin
                wdata       <= i_reg_wdata;
                reg_wen     <= i_reg_wen;
                reg_waddr   <= i_reg_waddr;
            `ifndef ysyx_050369_SOC
                pc          <= i_pc;
                inst        <= i_inst;
                dev         <= i_dev;
            `endif
            end
            else begin
                if (!as2wb_valid) begin
                    reg_wen     <= 'b0;
                    reg_waddr   <= 'b0;
                `ifndef ysyx_050369_SOC
                    pc          <= 'b0;
                    inst        <= 'b0;
                    dev         <= 'b0;
                `endif 
                end
            end
            
        end

    end
    RegisterFile reg_file(
        .clk        (clk),
        .wen        (reg_wen_w),
        .wdata      (wdata),
        .waddr      (reg_waddr),
        .raddra     (i_rs1),
        .raddrb     (i_rs2),    
        .rdata      (rd1),
        .rdatab     (rd2)
    );


`ifndef ysyx_050369_SOC
    reg      device_en1;
    wire o_run,o_device_en;
    wire device_en;
    assign o_run = (i_pc!=pc)&&(pc>32'h80000000)&&wb_ready;
    wire [31:0] inst_reg [4:0];
    import "DPI-C" function void get_inst(input logic [31:0] a0[]);
    assign   inst_reg[0] = inst;
    assign   inst_reg[1] = pc;
    assign   inst_reg[2] = i_pc;
    assign   inst_reg[3] = {31'b0,device_en};
    assign   inst_reg[4] = {31'b0,o_run};
    // assign   inst_reg[4] = {31'b0,o_raise_intr};
    always @(posedge clk ) begin
        get_inst(inst_reg);
    end 
    always @(posedge clk ) begin
        if (rst) begin
            device_en1 <= 'b0;
        end
        else begin
            device_en1 <= device_en;
        end
    end
    assign o_device_en = device_en||device_en1;
    assign device_en  =dev;
`endif
    
endmodule
